Delta-sigma modulators generally employ noise-shaping (filtering) and over-sampling to perform digital-to-analog (“D/A”) conversion at relatively high resolution for signals of modest bandwidth. The higher the order of the sigma-delta modulator, the further the quantization noise is pushed into the frequency band, away from the signal base band being converted. As such, DACs using delta-sigma modulators have become popular in a wide range of high precision applications, such as audio applications.
In a typical sigma-delta DAC architecture, a digital data signal (e.g. 16 bit audio data at a rate of 48 kHz) is upsampled by an interpolator at some multiple of the original data rate (e.g., at an upsampling ratio of 128 times (6.144 MHz/48 kHz)). The resulting oversampled digital signal is applied to a multi-bit sigma-delta modulator. The multi-bit digital data outputted by the modulator is applied to a multi-bit DAC, which may comprise a multi-bit current DAC (IDAC) to generate a multi-level analog current signal followed by a current-to-voltage converter to convert this analog current signal to an analog voltage signal. Finally, the stepped voltage signal is applied to a low pass filter to provide a smoothed analog output signal.
There are several problems with the known approaches to delta-sigma DACs, some of which are noted hereafter. First, known DACs require intrinsically low noise circuits, which are power and area hungry. Second, known approaches require the use of chopper stabilization to reduce low frequency 1/f noise in the CMOS circuits, which adds design complexity. Finally, these approaches require current sources with very high output impedances.